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cool solutions xemics sa, switzerland. tel: +41 32 720 51 70 fax: +41 32 720 57 70 e-mail: info@xemics.com web: www.xemics.com xx-xe88lc05 data sheet xe88lc05 ultra low-power microcontroller with adc and dacs for sensor conditioning general description the xe88lc05 is an ultra low-power microcontroller unit (mcu) associated with a versatile analo g -to-di g ital con- verter (adc) includin g a pro g rammable offset and g ain pre-amplifier (pga) and di g ital-to-analo g converters (dacs). xe88lc05 is available with on chip multiple-time-pro- g rammable (mtp) flash pro g ram memory. applications ? internet connected appliances ? portable, battery operated instruments ? piezoresistive brid g e sensors ? 4-20 ma bus sensors ? 0.5 - 4.5 v sensors ? hvac control ? motor control key product features ? ultra low-power mcu (300 a at 1 mips) ? low-volta g e operation (2.4 - 5.5 v supply volta g e) ? 22 kb (8 kw) mtp, 512 b ram ?volta g e or current output dacs ? buffered si g nal-dac (up to 16 bits) ? buffered bias-dac (up to 10 ma drive) ? low-power, hi g h resolution zoomin g adc ? up to 10 bits zoom ? up to 16 bits adc ? 4 x 2 or 7 x 1 pga-adc input multiplexer ?analo g matrix switchin g ? rc and crystal oscillators ? 5 reset, 16 interrupt, 8 event sources orderin g information nomenclature: (xx marks pre-production samples) ;(/&0( program memory m: mtp temperature i: -40 to 85 c tqfp64 package
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 2 detailed pin description pin description position function name second function name type 1 pa(0) testin input input of port a/ data input for test and mtp programming/ counter a input 2 pa(1) testck input input of port a/ data clock for test and mtp programming/ counter b input 3 pa(2) input input of port a/ counter c input/ counter capture input 4 pa(3) input input of port a/ counter d input/ counter capture input 5 pa(4) input input of port a 6 pa(5) input input of port a 7 pa(6) input input of port a 8 pa(7) input input of port a 9 pc(0) input/output input-output of port c 10 pc(1) input/output input-output of port c 11 pc(2) input/output input-output of port c 12 pc(3) input/output input-output of port c 13 pc(4) input/output input-output of port c 14 pc(5) input/output input-output of port c 15 pc(6) input/output input-output of port c 16 pc(7) input/output input-output of port c 17 pb(0) testout input/output/analog input-output-analog of port b/ data output for test and mtp programming/ pwm output table 1.2: pin-out of the xe88lc05 in tqfp64 pinout of the xe88lc05 in tqfp64 packa g e pa(0) pa(1) pa(2) pa(3) pa(4) pa(5) pa(6) pa(7) pc(0) pc(1) pc(2) pc(3) pc(4) pc(5) pc(6) pc(7) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 22 24 26 28 30 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 61 59 57 55 53 51 pb(0) pb(1) pb(2) pb(3) pb(4) pb(5) pb(6) pb(7) dab_out dab_ao_p dab_ao_m dab_ai_p dab_ai_m ac_r(0) ac_r(1) ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) ac_r(2) ac_r(3) oscin oscout reset vmult test vreg vss_vreg vss vbat das_out das_ai_p das_ai_m das_ao xemics dab_r_p dab_r_m xe88lc05mi n9k1444 9920 device type production packaging date lot identification
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 3 18 pb(1) input/output/analog input-output-analog of port b/ pwm output 19 pb(2) input/output/analog input-output-analog of port b 20 pb(3) sou input/output/analog input-output-analog of port b, output pin of usrt 21 pb(4) scl input/output/analog input-output-analog of port b/ clock pin of usrt 22 pb(5) sin input/output/analog input-output-analog of port b/ data input or input-output pin of usrt 23 pb(6) tx input/output/analog input-output-analog of port b/ emission pin of uart 24 pb(7) rx input/output/analog input-output-analog of port b/ reception pin of uart 25 dab_r_p analog positive reference of bias dac 26 dab_r_m analog negative reference of bias dac 27 dab_out analog output of bias dac 28 dab_ao_p analog highest potential output of bias dac buffer 29 dab_ao_m analog lowest potential output of bias dac buffer 30 dab_ai_p analog positive input of bias dac buffer 31 dab_ai_m analog negative input of bias dac buffer 32 not connected spare pins to be connected to negative power supply 33 test/vhigh vhigh special test mode/high voltage for mtp programming 34 not connected spare pins to be connected to negative power supply 35 ac_r(3) analog highest potential node for 2nd reference of adc 36 ac_r(2) analog lowest potential node for 2nd reference of adc 37 ac_a(7) analog adc input node 38 ac_a(6) analog adc input node 39 ac_a(5) analog adc input node 40 ac_a(4) analog adc input node 41 ac_a(3) analog adc input node 42 ac_a(2) analog adc input node 43 ac_a(1) analog adc input node 44 ac_a(0) analog adc input node 45 ac_r(1) analog highest potential node for 1st reference of adc 46 ac_r(0) analog lowest potential node for 1st reference of adc 47-50 not connected spare pins to be connected to negative power supply 51 das_out analog output of signal dac 52 das_ai_p analog positive input of signal dac buffer 53 das_ai_m analog negative input of signal dac buffer 54 das_ao analog output of signal dac buffer 55 vbat power positive power supply 56 vss power negative power supply, connected to substrate 57 vss_reg power digital negative power supply, must be equal to vss 58 vreg analog regulated supply 59 not connected spare pins to be connected to negative power supply 60 vmult analog pad for optional voltage multiplier capacitor 61 reset input reset pin (active high) 62 oscout ptck analog/input connection to xtal/ peripheral clock for test and mtp programming 63 oscin ck_cr analog/input connection to xtal/ coolrisc clock for test and mtp programming 64 - - do not connect, or vss pin description position function name second function name type table 1.2: pin-out of the xe88lc05 in tqfp64
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 4 xe88lc05xi electrical characteristics note: 1) power supply: 2.4 v - 5.5 v, at 27c; min volta g e of xx version may be hi g her, max frequency of current xx version is 2 mhz note: 2) temperature < 85c note: 3) output not loaded. note: 4) current requirement can be divided by a factor of 2 or 4 by reducin g the speed accordin g ly. note: 5) more cycles possible durin g development, with restraint retention operation conditions min typ max unit remarks power supply rom version 2.4 5.5 v mtp version 2.4 5.5 v current requirement cpu running at 1 mips 310 ua 1 cpu running at 32 khz on xtal, rc off 10 ua 1 cpu halt, timer on xtal, rc off 1ua 1 cpu halt, timer on xtal, rc ready 1.7 ua 1 cpu halt, xtal off timer on rc at 100 khz 1.4 ua 1 cpu halt, adc 12 bits at 4 khz 200 ua 1,4 cpu halt, adc 12 bits at 4 khz, pga gain 100 250 ua 1,4 cpu at 1 mips, adc 12 bits and dac 10 bits at 4 khz 660 ua 1,3,4 cpu at 1 mips, adc 12 bits and dac 10 bits at 4 khz, pga gain 10 685 ua 1,3,4 cpu at 1 mips, adc 12 bits and dac 10 bits at 4 khz, pga gain 100 710 ua 1,3,4 cpu at 1 mips, adc 12 bits and dac 10 bits at 4 khz, pga gain 1000 785 ua 1,3,4 voltage level detection 15 ua mtp prog. voltage 10.3 10.8 v erase time 3 30 s write/erase cycles 10 100 5 data retention 10 year 2 current requirement of the xe88lc05
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 5 cpu the xe88lc05 cpu is a low power risc core. it has 16 internal re g isters for efficient implementation of the c com- piler. its instruction set is made of 35 g eneric instructions, all coded on 22 bits, with 8 addressin g modes. all instruc- tions are executed in one clock cycle, includin g conditional jumps and 8x8 multiplication. a complete tool suite for development is available from xemics, includin g pro g rammer, c-compiler, assembler, simulator, linker, all inte g rated in a modern and efficient g raphical user interface. memory organisation the cpu uses a harvard architecture, so that memory is or g anised in two separated fields: pro g ram memory and data memory. as both memory are separated, the central processin g unit can read/write data at the same time it loads an instruction. peripherals and system control re g isters are mapped on data memory space. pro g ram memory is made in one pa g e (pro g ram pa g e full size is 65536 instructions). data is made of several 256 bytes pa g es. program memory the pro g ram memory is implemented as multiple time pro g rammable (mtp) flash memory. the power consumption of mtp is linear with the access frequency (no si g nificant static current). memory sizes: ? flash mtp: 8192 x 22 bits (= 22 kbytes) block size address mtp 8192 x 22 h0000 - h1fff program addresses memory or g anization cpu program memory registers peripherals ram program address bus data address bus 22 bits wide 8 bits wide cpu registers instruction pipeline 8k instructions 512 bytes
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 6 data memory the data memory is implemented as static random-access memory (ram). the size is 512 x 8 bits plus 8 low pow- er re g isters that require very low current when addressed, pro g rams usin g these re g isters instead of ram will spare even more current. note: the re g isters in data memory are not related to the cpu re g isters. peripherals mapping peripherals the xe88lc05 includes usual microcontroller peripherals and some other blocks more specific to low-volta g e or mixed-si g nal operation. they are 3 parallel ports, one input port (a), one io and analo g port (b) with analo g switch- in g capabilities and one g eneral purpose io port (c). a watchdo g is available, connected to a prescaler. four 8-bit counters, with capture, pwm and chainin g capabilities are available. the uart can handle transmission speeds as hi g h as 38kbaud. low-power low-volta g e blocks include a volta g e level detector, two oscillators (one internal 0.1-4 mhz rc oscillator and a 32 khz crystal oscillator) and a specific re g ulation scheme that lar g ely uncouples current requirement from external power supply (usual cmos asics require much more current at 5.5 v than they need at 2.4 v. this is not the case for the xe88lc05). analo g blocks: acquisition path, bias dac and si g nal dac are defined below. all these blocks operate on 2.4 - 5.5 v power supply ran g e. block size address lp ram 8 x 8 h0000 - h0007 ram 512 x 8 h0080 - h027f ram addresses block size address page lp ram 8x8 h0000-h0007 page 0 system control 16x8 h0010-h001f port a 8x8 h0020-h0027 port b 8x8 h0028-h002f port c 4x8 h0030-h0033 port d 4x8 h0034-h0037 mtp 4x8 h0038-h003b event 4x8 h003c-h003f interrupts control 8x8 h0040-h0047 reserved 8x8 h0048-h004f uart 8x8 h0050-h0057 counters 8x8 h0058-h005f zooming adc 8x8 h0060-h0067 reserved 12x8 h0068-h0073 dacs 8x8 h0074-h007b other (vld) 4x8 h007c-h007f ram1 128x8 h0080 - h00ff ram2 256x8 h0100 - h01ff page 1 ram3 128x8 h0200 - h027f page 2 peripherals addresses
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 7 zooming adc principle the fully differential acquisition chain is formed of a pro g rammable g ain (0.5 - 1000) and offset amplifier and a pro- g rammable speed and resolution adc (example: 12 bits at 4 khz, 16 bits at 1 khz). it can handle inputs with very low full scale si g nal and lar g e offsets. input selection is made from 1 of 4 differential pair or 1 of seven sin g le si g nal versus ac_a(0). reference is chosen from the 2 differential references. acquisition path offset can be suppressed by invertin g input polarity. the g ain of each amplifier is pro g rammed individually. each amplifier is powered on and off on command to mini- mize the total current requirement. all blocks can be set to low frequency operation and lower their current require- ment by a factor 2 or 4. the adc can run continuously (end of conversion si g nalled by an interrupt, event or by poolin g the ready bit), or it can be started on request. input signal multiplexing there are 8 inputs named ac_a[0] to ac_a[7]. inputs can be used either as four differential channels (vin1=ac_a[1]-ac_a[0], , vin4=ac_a[7]-ac_a[6]) or ac_a[0] can be used as a common reference, providin g 7 si g nal paths (ac_a[1]-ac_a[0], , ac_a[7]-ac_a[0]), all referred to ac_a[0]. default input is vin1. on top of these settin g s, inputs can be crossed or not. all multiplexin g combinations are summarised in the followin g table (see table 1.3) : uni/bi-polar sign channel selection selected differential input amux(4) amux(3) amux(2) amux(1) amux(0) vin- vin+ 0 0 unused 0 0 a(0) a(1) 0 1 a(2) a(3) 1 0 a(4) a(5) 1 1 a(6) a(7) 1 unused 0 0 a(1) a(0) 0 1 a(3) a(2) 1 0 a(5) a(4) 1 1 a(7) a(6) table 1.3: amux selection acquisition channel block dia g ram jdlq riivhw jdlq riivhw jdlq prgh rxwsxw frgh lqsxw vhohfwlrq $'& $&b$ $&b$ $&b$ $&b$ $&b$ $&b$ $&b$ $&b$ $&b5 $&b5 $&b5 $&b5 uhihuhqfh vhohfwlrq
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 8 input reference multiplexing one must select one of two differential si g nal as reference si g nal (vref1=ac_r[1]-ac_r[0], vref2=ac_r[3]- ac_r[2]). default is vref1. amplifier chain the 3 sta g es transfer functions are: vd3 = gd3 . vd2 - gdoff3 . vref vd2 = gd2 . vd1 - gdoff2 . vref vd1 = gd1 . vin where: vin=selected input volta g e vref=selected reference volta g e vd1=differential volta g e at the output of first amplifier vd2=differential volta g e at the output of second amplifier vd3=differential volta g e at the output of third amplifier gd1=differential g ain of sta g e 1 gd2=differential g ain of sta g e 2 gd3=differential g ain of sta g e 3 gdoff2= offset g ain of sta g e 2 gdoff3=offset g ain of sta g e 3 and therefore the whole transfer function is: vout of pga = vd3 = gd3 . gd2 . gd1 . vin - (gdoff3 + gdoff2 . gd3) . vref note: as the offset compensation is realized to g ether with the amplification on the same summin g node, the only volta g es that have to stay within the supplies are vref and the vd i . gd i . vd i-1 and gdoff i . vref can be lar g er without any saturation. note: all sta g es use a fully differential architecture and all g ain and offset settin g s are realized with ratios of capacitors. note: as the adc also provides a g ain (2 nominal), the total chain transfer function is: each sta g e is called pgai. features of these sta g es are: 1 0 000a(0)a(0) 001a(0)a(1) 010a(0)a(2) 011a(0)a(3) 100a(0)a(4) 101a(0)a(5) 110a(0)a(6) 111a(0)a(7) 1 000a(0)a(0) 001a(1)a(0) 010a(2)a(0) 011a(3)a(0) 100a(4)a(0) 101a(5)a(0) 110a(6)a(0) 111a(7)a(0) uni/bi-polar sign channel selection selected differential input amux(4) amux(3) amux(2) amux(1) amux(0) vin- vin+ table 1.3: amux selection () 3 2 3 2 1 2 3 2 _ gd gdoff gdoff vref vin gd gd gd out data + - =
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 9 ? gain can be chosen between 1 and 10 (between 0 and 10 for pga3) ? offset can be compensated for in pga2 (a little) and in pga3 (to a lar g e extent) ? granularity of settin g s is rou g h for pga1, medium for pga2, fine for pga3 ? zero, one or two or three of the pga sta g es can be used. a functional example of one of the sta g es is g iven on ta g 1.1. 1.1.1 pga 1 note: 1) measured with block connected to inputs throu g h amux block. normalized input samplin g frequency for input impedance is 512 khz. this fi g ure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. note: 2) input referred rms noise is 10 uv per input sample. this corresponds to 18 nv/sqrt(hz) for fs = 512 khz. 1.1.2 pga2 note: 1) measured with block connected to inputs throu g h amux block. normalized input samplin g frequency for input impedance is 512 khz. this fi g ure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. symbol description min typ max unit comments gd1 pga1 signal gain 1 10 - gd1 = 1 or 10 gd_preci precision on gain settings -5 +5 % gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 512 khz zin1 input impedance 150 k w 1 zin1p input impedance for gain 1 1500 k w 1 vn1 input referred noise 18 nv/ sqrt(hz) 2 table 1.4: pga1 performances sym description min typ max unit comments gd2 pga2 signal gain 1 10 - gd2 = 1, 2, 5 or 10 gdoff2 pga2 offset gain -1 1 fs gdoff2_step gdoff2(code+1) C gdoff2(code) 0.18 0.2 0.22 - gd_preci precision on gain settings -5 +5 % valid for gd2 and gdoff2 gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 512 khz zin2 input impedance 150 k w 1 vn2 input referred noise 36 nv/ sqrt(hz) 2 table 1.5: pga2 performances fi g ure 1.1: pga sta g e principle implementation vref vin vout
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 10 note: 2) input referred rms noise is 26uv per sample.this corresponds to 36 nv/sqrt(hz) max for fs = 512 khz. 1.1.3 pga3 note: 1) measured with block connected to inputs throu g h amux block. normalized input samplin g frequency for input impedance is 512 khz. this fi g ure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. note: 2) input referred rms noise is 26uv per sample. this corresponds to 36 nv/sqrt(hz) max for fs = 512 khz. adc 1.1.4 input-output relation the adc block is used to convert the differential input si g nal into a 16 bits 2s complement output format. the output code corresponds to the ratio: smax bein g the number of samples used to g enerate one output sample per elementary conversion. smax is set by osr on regaccfg0 . vref can be selected up to the power supply rails and must be positive. the 2s complement output code correspond- in g is g iven in hexadecimal notation by 8000 (ne g ative full scale) and 7fff (positive full scale). code outside the ran g e are saturated to the closest full scale value. the output code is normalized into a 16 bits format. first non si g nificant bit is forced to 1, further non si g nifant bits are forced to 0. 1.1.5 operation mode the mode can be either on request or continuously runnin g . in the on request mode, after a request, an initialization sequence is performed, then an al g orithm is applied and an output code is produced. the converter is idle until the next request. in the continuously runnin g mode, an internal conversion request is g enerated each time a conversion is finished, so that the converter is never idle. the output code is updated at a fixed rate correspondin g to 1/tout, with tout bein g the conversion time. sym description min typ max unit comments gd3 pga3 signal gain 0 10 - gdoff3 pga3 offset gain -5 5 fs gd3_step gd3(code+1) - gd3(code) 0.075 0.08 0.085 - gdoff3_step gdoff2(code+1) C gdoff2(code) 0.075 0.08 0.085 - gd_preci precision on gain settings -5 +5 % valid for gd3 and gdoff3 gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 512 khz zin3 input impedance 150 k w 1 vn3 input referred noise 36 nv/ sqrt(hz) 2 table 1.6: pga3 performances register data msb lsb regacoutlsb bit 5 bit 4 bit 3 bit 2 bit 1 1 0 0 regacoutmsb sign bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 table 1.7: output code exemple, for 13 bits resolution (osr: h11, nelconv: h01) output code = vin vref smax + 1 smax .
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 11 1.1.6 conversion sequence the whole conversion sequence is basically made of an initialisation, a set of nelconv elementary incremental con- versions and finally a termination phase( n umconv is set by 2 bits on regaccfg0 ). the result is a mean of the results of the elementary conversions. note: n umconv elementary conversions are performed, each elementary conversion bein g made of smax input samples. n umconv = 2 nelconv smax = 8*2 osr durin g the elementary conversions, the operation of the converter is the same as in a si g ma delta modu- lator. durin g one conversion sequence, the elementary conversions are alternatively performed with direct and crossed pga-adc differential inputs, so that when two elementary conversions or more are per- formed, the offset of the converter is cancelled. note: the sizin g of the decimation filter puts some limits on the total number of conversions and it is not possible to combine the maximum number of elementary conversions with the maximum oversamplin g (see the nel- conv*smax specification). some additional clock cycles (n init +n end ) clock cycles are required to initiate and terminate the conversion prop- erly. 1.1.7 conversion duration the conversion time is g iven by : t out = (2 nelconv *(8*2 osr +1) + (n init + n end )) / fs 1.1.8 resolution as far as it is not limited by thermal noise and internal re g isters width, the resolution is g iven by : resolution (in bits) = 6 + 2*osr + nelconv 1.1.9 adc performances sym description min typ max unit comments vinr input range -0.5 0.5 vref resol resolution 12 bits 1 nresol numerical resolution 16 bits 4 inl integral non-linearity 4 lsb 1,3, lsb at 12bits table 1.8: adc performances fi g ure 1.2: conversion sequence. smax is the oversamplin g rate. start end 1st elementary conversion 2nd elementary conversion elementary conversion elementary conversion conversion index 1 2n umconv -1 n umconv input 12 smax 12 smax 12 smax sample
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 12 note: 1) resolution specification also includes thermal noise and differential non-linearity (dnl) for a reference si g nal of 2.4 v. it is defined for default operatin g mode ( see default operation mode (not yet implement- ed) on pa g e13.) note: 2) only powers of 2 note: 3) inl is defined as the deviation of the dc transfer curve from the best fit strai g ht line. this specification holds over 100% of the full scale. note: 4) nresol is the maximal readable resolution of the di g ital filter. input noise may be hi g her than nresol. control part startin g a convention a conversion is started each time start or def is set. pgas are reset after each writin g operation to re g isters regaccfg1 to regaccfg5 . when usin g the pgas, one has to start the adcs after a pga common-mode stabili- sation delay. this is done by writin g bit start several cycles after pga settin g s modification. delay between pga start and adc start should be equivalent to smax number of cycles. end of a conversion the end of the conversion is marked by the return to zero of busy bit, and, if set, by the g eneration of adc interrupt. busy bit = 0 is not sufficient to denote the end of the conversion, as the adc needs some clock cycles to set it to one at the conversion be g innin g . only the transition from 1 to 0 denotes the end of conversion. for low power or low noise applications, one should prefer to use the interruption as the processor can g o to halt between conversion start and conversion end. clocks g eneration peripheral clock (psck) can be chosen amon g four prescaler clocks (bit fin of regaccfg2 ), see table 1.10, derived from the xe8000 rc oscillator. the clock of the acquisition path (fs) is derived from the peripheral clock. fs = psck / 4 fs sampling frequency 10 512 khz smax oversampling ratio 8 1024 - 2 n umconv number of elementary conversions in incremental mode 18-2 ninit number of periods for incremental conversion initialization 5- nend number of periods for incremental conversion termination 5- sym description min typ max unit comments table 1.8: adc performances
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 13 acquisition of a sample default operation mode (not yet implemented) the def bit ( regaccfg5 ) allows the use of the adc in a default mode without any g ain nor offset adjustment (see values in the ri g ht column of table 1.10). this default mode is used in specifications to define resolution and inl. the only action to launch the operation of the peripheral is in this case to write a x1xx xxxx at address 111. vmux and amux are written at the same time and are not reset to default value. busy is not affected. the only way to stop a runnin g conversion before completion is to shut the adc down writin g 0000 in enable ( regaccfg1 ). re g isters ei g ht re g isters control this peripheral. two re g isters are for the data output, six for peripheral g eneral set-up. re g - isters are defined in table 1.9 and table 1.10. register data regacoutlsb adc_out_l regacoutmsb adc_out_h table 1.9: peripheral register memory map fi g ure 1.3: acquisition flow use default mode write in regaccfg5 yes no use pga write in regaccfg1-5 yes no and modifiy pga wait for pga stable start adc by writing regaccfg0 wait for adc ready read adc results
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 14 regaccfg0 start nelconv osr cont reserved regaccfg1 ib_amp_adc ib_amp_pga enable regaccfg2 fin pga2_gain pga2_off regaccfg3 pga1_ gain pga3_gain regaccfg4 reserved pga3_off regaccfg5 busy def amux vmux name register rm description default (reset and def mode) adc_out(15:0) regacoutlsb regacoutmsb r data output 0000h amux(4:0) regaccfg5 wr selection of pga inputs 00000 (reset only) busy regaccfg5 r 1 : conversion is in progress 0 : data is available 0 cont regaccfg0 wr 1 : continuous operation. 0 : one shot mode 0 def regaccfg5 wr0 default operation bit 1: all registers but vmux and amux are reset and default values are used 0: normal operation n/a enable(3:0) regaccfg1 wr bit3 : pga3, bit2 : pga2, bit1 : pga1, bit 0 : adc if a bit is 1, the block is powered. if not, the block is switched off and all internal digital signals are reset. concerning the pgas, enable=0 means also that inputs and outputs are wired together and that the acquisition chain is not perturbed by the block. 0000 fin(1:0) regaccfg2 wr 00 : rc = psck = 4 fs 01 : rc / 2 = psck = 4 fs 10 : rc / 8 = psck = 4 fs 11 : rc / 32 = psck = 4 fs rem: do not select an fs clock that is faster than 512 khz. 00 ib_amp_pga(1:0) regaccfg1 wr pga amplifiers biasing current reduction factor 00 : current magnification factor = 0.25 01 : current magnification factor = 0.5 10 : current magnification factor = 0.75 11 : current magnification factor = 1 11 ib_amp_adc(1:0) regaccfg1 wr adc amplifiers biasing current reduction factor. tuning identical to ib_amp_pga 11 nelconv(1:0) regaccfg0 wr number of elementary conversions 00 : 1 conversion, 01 : 2 conversions 10 : 4 conversions, 11 : 8 conversions 01 osr(2:0) regaccfg0 wr oversampling ratio. defined as fs/fout. o sr = 8*2 osr(2:0) . 000 : oversampling = 8, ..., 111 : oversampling = 1024 010 pga1_gain regaccfg3 wr signal gain of first pga stage (gd1) 1 : nominal gain is 10. 0 : nominal gain is 1 0 pga2_gain(1:0) regaccfg2 wr signal gain of second pga stage (gd2) 11 : nominal gain is 10 10 : nominal gain is 5 01 : nominal gain is 2 00 : nominal gain is 1 00 pga2_off(3:0) regaccfg2 wr offset gain of second pga stage (gdoff2) bit 3: offset sign (0 : gdoff2 > 0, 1 : gdoff2 < 0) bits (2:0) : offset amplitude 01x1 : gdoff2 = 1.0 nominal, 0100 : gdoff2 = 0.8 nominal, 0011 : gdoff2 = 0.6 nominal, ..., 0000 : gdoff2 = 0.0 nominal, 1001 : gdoff2 = -0.2 nominal, ..., 11x1 : gdoff2 = -1.0 nominal 0000 pga3_gain(6:0) regaccfg3 wr signal gain of third stage (gd3) gd3 = 0.08*pga3_gain(6:0) nominal values : 0 (000 0000), ..., 10 (111 1000) 000 1100 pga3_off(6:0) regaccfg4 wr offset gain of third stage (gdoff3) bit 6: offset sign (0 : gdoff3 > 0, 1 : gdoff3 < 0) gdoff3 = 0.08*pga3_off(5:0), maximum = 5.04 nominal values : -5.04 (111 1111), 0 (x00 0000), +5.04 (011 1111) 000 0000 start regaccfg0 wr0 writing a 1 in start bit restarts the adc. it does not affect the pgas. 0 table 1.10: peripheral register memory map, bits description register data table 1.9: peripheral register memory map
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 15 dacs see xemics application note an8000.03 for detailed information about the xe88lc05 dacs. bias dac the bias dac is a low resolution (8 bits) dac with a buffer perfectly adapted to sensor brid g e bias. it can be used to bias a brid g e in current (fi g ure) or in volta g e by choosin g the pins connection. the bias dac itself is built off a series of resistors which two extremes are available outside the chip, so that one can connect it to an external source when the output of the dac should not be ratiometric to the power supply. test regaccfg0 reserved 0 vmux regaccfg5 wr vref selection multiplexer 0 : vref0 is used, 1 : vref1 is used 0 (reset only) name register rm description default (reset and def mode) table 1.10: peripheral register memory map, bits description current controlled brid g e bias signal reference xe88xx d a c o n t r o l amp '$%b2xw '$%b$,s '$%b$2s '$%b$,p '$%b$2p ;(/&
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 16 signal dac the si g nal dac is build around a pro g rammable dac and a buffer. it can g enerate fast (up to 64 khz) or hi g h res- olution (resolution up to 16 bits) output. the output can be controlled in current or volta g e. 4-20ma loop includin g the circuit (and brid g e) current consumption xe88xx d a c o n t r o l amp 4-20ma '$6b2xw '$6b$,p '$6b$2 '$6b$,s 9edw 966 9 uhjxodwru ;(/&
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 17 xe8000 family features the main characteristics of the xe8000 mcu family is ? ultra low power operation ? low volta g e operation (1.2 v for the xe88lc04, xe88lc06 and xe88lc07, 2.4 v for the others) ?hi g h efficiency cpu ? 1 instruction per clock cycle, for all instructions ? 22 bits wide instructions ?inte g rated 8x8 -> 16 bits multiplier ? all instructions on one pa g e ? 8 bits data bus ? 8 addressin g modes ? mtp (multiple time pro g rammable) memory available ? dual clock (x-tal and/or rc) ? each peripheral can be set on/off individually for minimal power consumption ? uart ?watch do g ? 4x8 bits timers with pwm ability ? advanced acquisition path ? fully differential analo g si g nal path on si g nal and reference ? 4x2 or 7x1 + 1 si g nal input ? 2x2 reference input ? 0.5 - 1000 pro g rammable g ain amplifier ?offset pro g rammed over +- 10 full scale ? 5 - 16 bits resolution adc ? low speed modes with reduced bias current for minimal power consumption ? bias and si g nal dacs for resistive brid g e sensin g and analo g output ? complete development tools usin g windows95 or nt g raphical interface ? assembler ? ansi-c compiler ? source level debu gg er ? current and memory usa g e monitorin g (profiler) ? cpu simulator ? cpu emulator xe8000hace ? pro g rammer and starter kit (xe88lc01prostart) ? hardware emulators (works with xe8000hace, in preparation) family the xe8000 family ultra low-power microcontroller is made of several members, all usin g the same microprocessor core and differin g by the peripherals available. the xe88lc01 is a low power sensin g microcontroller, based on the xe88lc03, with an advanced acquisition path includin g differential pro g rammable g ain amplifiers and a hi g h resolution analo g to di g ital converter. its main appli- cations are datalo gg ers and process control. the xe88lc02 is a low power sensin g microcontroller, based on the xe88lc06 with the analo g part of the xe88lc01, with an additional lcd driver. its main applications are meterin g and datalo gg ers. tthe xe88lc03 is a low power, low volta g e, g eneral purpose microcontroller. its main points are the very efficient coolrisc core, the low volta g e function and the real time clock. its main applications are low volta g e control and supervision.
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 18 the xe88lc04 is a low power, low volta g e, g eneral purpose microcontroller, based on the xe88lc06, with an ad- ditional lcd driver. its main points are the very efficient coolrisc core, the low volta g e function and the real time clock. its main applications are low volta g e control and supervision. the xe88lc05 is a low power sensin g microcontroller, based on the xe88lc01, with analo g outputs. its main ap- plications are piezoresistive sensors and 4 - 20 ma loops systems. the xe88lc06 is an improved xe88lc03, with 4 low power analo g comparators. its main applications are low volt- a g e control and supervision. the xe88lc07 is a smaller and even lower power microcontroller, based on the xe88lc06, with less memory. xe88lc01 xe88lc02 xe88lc03 xe88lc04 xe88lc05 supply voltage 2.4 - 5.5 v 2.4 - 5.5 v 2.4 - 5.5 v 1.2- 5.5 v for rom 2.4 - 5.5 v for mtp 2.4 - 5.5 v max speed 2 mips 4 mips 2 mips 4 mips at 2.4 v 2 mips operating temperature -40 - 85 c -40 - 85 c -40 - 125 c -40 - 85 c -40 - 85 c -40 - 125 c -40 - 85 c cpu coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier program memory 8k instructions = 22 kb rom or mtp 8k instruction = 22 kb rom or mtp 8k instructions = 22 kb rom or mtp 8k instructions = 22 kb rom or mtp 8k instructions = 22 kb rom or mtp data memory 512 + 8 bytes 768 + 8 bytes 512 + 8 bytes 768 + 8 bytes 512 + 8 bytes port a 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt port b 8 input/output and analog 8 input/output and analog 8 input/output and analog 8 input/output and analog 8 input/output and analog port c 8 input/output 8 input/output 4 to 8 input/output 4 to 8 input/output 8 input/output watchdog timer yes yes yes yes yes general purpose timers with pwm 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits uart yes yes yes yes yes 2-3 wires serial interface transition detection + software transition detection + software transition detection + software transition detection + software transition detection + software voltage level detector yes yes yes yes yes oscillators 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc lcd drivers 120 segments 120 segments analog mux port b and 4x2 or 7x1+1 port b and 4x2 or 7x1+1 port b port b port b and 4x2 or 7x1+1 lp comparators 4 4 pga gain 0.5 - 1000 gain 0.5 - 1000 gain 0.5 - 1000 adc 5 - 16 bits resolution 5 - 16 bits resolution 5 - 16 bits resolution dac pwm pwm pwm pwm pwm 8 bit bias dac, 4 - 16 bits signal dac package tqfp44, die so28, tqfp32, die tqfp64, die availability yes samples q2/01 yes samples q2/01 yes table 1.11: list of the xe8000 family members functions
low-power microcontroller xx-xe88lc01 xx/d010-060 product preliminary specification pa g e 19 contacting xemics you can contact xemics at xemics sa tel: +41 32 720 5170 fax: +41 32 720 5770 e-mail: info@xemics.com you will find more information about the xe88lc05 and other xemics products, as well as the addresses of our representatives and distributors for your re g ion on www.xemics.com. copyri g ht xemics all ri g hts are reserved. reproduction whole or in part is prohibited without the prior written consent of the copyri g ht owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be chan g ed without notice. no liability will be accepted by the publisher for any con- sequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property ri g hts.printed in switzerland.

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